UPD78F4218AYGC-8EU datasheet(35/60 Pages) NEC

Part #	UPD78F4218AYGC-8EU

Description	MOS INTEGRATED CIRCUIT

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Data Sheet U14125EJ1V0DS00

35

µµµµPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Serial Operation (TA =

−−−−40 to +85°°°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)

(a) 3-wire serial I/O mode (SCK: Internal clock output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

≤ VDD ≤ 5.5 V

800

ns

SCK cycle time

tKCY1

3,200

ns

2.7 V

≤ VDD ≤ 5.5 V

350

ns

SCK high-/low-level width

tKH1,

tKL1

1,500

ns

2.7 V

≤ VDD ≤ 5.5 V

10

ns

SI setup time (to SCK

↑)tSIK1

30

ns

SI hold time (from SCK

↑)tKSI1

40

ns

SO output delay time

(from SCK

↓)

tKSO1

30

ns

(b) 3-wire serial I/O mode (SCK: External clock input)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

≤ VDD ≤ 5.5 V

800

ns

SCK cycle time

tKCY2

3,200

ns

2.7 V

≤ VDD ≤ 5.5 V

400

ns

SCK high-/low-level width

tKH2

tKL2

1,600

ns

2.7 V

≤ VDD ≤ 5.5 V

10

ns

SI setup time (to SCK

↑)tSIK2

30

ns

SI hold time (from SCK

↑)tKSI2

40

ns

SO output delay time

(from SCK

↓)

tKSO2

30

ns

(c) UART mode

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

≤ VDD ≤ 5.5 V

417

ns

2.7 V

≤ VDD < 4.5 V

833

ns

ASCK cycle time

tKCY3

1,667

ns

4.5 V

≤ VDD ≤ 5.5 V

208

ns

2.7 V

≤ VDD < 4.5 V

416

ns

ASCK high-/low-level width

tKH3

tKL3

833

ns

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UPD78F4218AYGC-8EU Datasheet(PDF) 35 Page - NEC

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