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UPD78F4218AGF-3BA Datasheet(PDF) 33 Page - NEC |
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UPD78F4218AGF-3BA Datasheet(HTML) 33 Page - NEC |
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33 / 60 page  Data Sheet U14125EJ1V0DS00 33 µµµµPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY AC Characteristics (1) Read/write operation (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD = 5.0 V ±10% 0.5T − 2ns VDD = 3.0 V ±10% 0.5T − 12 ns Address active time from RD ↑ tDRA VDD = 2.0 V ±5% 0.5T − 35 ns VDD = 5.0 V ±10% 0.5T − 9ns VDD = 3.0 V ±10% 0.5T − 9ns Delay time from RD ↑ to ASTB↑ tDRST VDD = 2.0 V ±5% 0.5T − 40 ns VDD = 5.0 V ±10% (1.5 + n)T − 25 ns VDD = 3.0 V ±10% (1.5 + n)T − 30 ns RD low-level width tWRL VDD = 2.0 V ±5% (1.5 + n)T − 25 ns VDD = 5.0 V ±10% (1 + a)T − 24 ns VDD = 3.0 V ±10% (1 + a)T − 34 ns Delay time from address to WR ↓ tDAW VDD = 2.0 V ±5% (1 + a)T − 70 ns VDD = 5.0 V ±10% 0.5T − 14 ns VDD = 3.0 V ±10% 0.5T − 14 ns Address hold time (from WR ↑)tHRD VDD = 2.0 V ±5% 0.5T − 14 ns VDD = 5.0 V ±10% 0.5T + 15 ns VDD = 3.0 V ±10% 0.5T + 30 ns Delay time from ASTB ↓ to data output tDSTOD VDD = 2.0 V ±5% 0.5T + 240 ns VDD = 5.0 V ±10% 0.5T − 30 ns VDD = 3.0 V ±10% 0.5T − 30 ns Delay time from WR ↓ to data output tDWOD VDD = 2.0 V ±5% 0.5T − 30 ns VDD = 5.0 V ±10% 0.5T − 9ns VDD = 3.0 V ±10% 0.5T − 9ns Delay time from ASTB ↓ to WR↓ tDSTW VDD = 2.0 V ±5% 0.5T − 20 ns VDD = 5.0 V ±10% (1.5 + n)T − 20 ns VDD = 3.0 V ±10% (1.5 + n)T − 25 ns Data setup time (to WR ↑)tSODWR VDD = 2.0 V ±5% (1.5 + n)T − 70 ns VDD = 5.0 V ±10% 0.5T − 14 ns VDD = 3.0 V ±10% 0.5T − 14 ns Data hold time (from WR ↑)tHWOD VDD = 2.0 V ±5% 0.5T − 50 ns VDD = 5.0 V ±10% 0.5T − 9ns VDD = 3.0 V ±10% 0.5T − 9ns Delay time from WR ↑ to ASTB↑ tDWST VDD = 2.0 V ±5% 0.5T − 30 ns VDD = 5.0 V ±10% (1.5 + n)T − 25 ns VDD = 3.0 V ±10% (1.5 + n)T − 30 ns WR low-level width tWWL VDD = 2.0 V ±5% (1.5 + n)T − 30 ns Remark T: tCYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) |
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