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UPD78F4218A Datasheet(PDF) 37 Page - NEC

Part # UPD78F4218A
Description  MOS INTEGRATED CIRCUIT
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD78F4218A Datasheet(HTML) 37 Page - NEC

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Data Sheet U14125EJ1V0DS00
37
µµµµPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Other Operations (TA =
−−−−40 to +85°°°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
NMI high-/low-level width
tWNIL
tWNIH
10
µs
Interrupt input high-/low-level width
tWITL
tWITH
INTP0 to INTP6
100
ns
RESET high-/low-level width
tWRSL
tWRSH
10
µs
Clock Output Operation (TA =
−−−−40 to +85°°°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
PCL cycle time
tCYCL
4.5 V
≤ VDD ≤ 5.5 V, nT
80
31,250
ns
PCL high-/low-level width
tCLL
tCLH
4.5 V
≤ VDD ≤ 5.5 V, 0.5T − 10
30
15,615
ns
4.5 V
≤ VDD ≤ 5.5 V
5
ns
2.7 V
≤ VDD < 4.5 V
10
ns
PCL rise/fall time
tCLR
tCLF
1.9 V
≤ VDD < 2.7 V
20
ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)
n: Divided frequency ratio set by software in the CPU
• When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128
• When using the subsystem clock: n = 1


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