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74AUP1G32GM Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G32GM Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 3 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 6. Functional diagram 7. Pinning information 7.1 Pinning 7.2 Pin description Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram mna164 B A Y 2 1 4 mna165 4 ≥1 2 1 mna166 B A Y Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) 32 BVCC A GND Y 001aab640 1 2 3 5 4 32 A 001aab641 B GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 Table 4: Pin description Symbol Pin Description TSSOP5 XSON6 B 1 1 data input B A 2 2 data input A GND 3 3 ground (0 V) Y 4 4 data output Y n.c. - 5 not connected VCC 5 6 supply voltage |
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