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IDT74LVC16373APF Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT74LVC16373APF Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 6 page  5 EXTENDEDCOMMERCIALTEMPERATURERANGE IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH Open VLOAD GND VCC Pulse Generator D.U.T. 500 Ω 500 Ω CL RT VIN VOUT (1, 2) LVC Link INPUT VIH 0V VOH VOL tPLH1 tSK (x) OUTPUT 1 OUTPUT 2 tPHL1 tSK (x) tPLH2 tPHL2 VT VT VOH VT VOL tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 LVC Link SAME PHASE INPUT TRANSITION OPPOSITE PHASE INPUT TRANSITION 0V 0V VOH VOL tPLH tPHL tPHL tPLH OUTPUT VIH VT VT VIH VT LVC Link DATA INPUT 0V 0V 0V 0V tREM TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tSU tH tSU tH VIH VT VIH VT VIH VT VIH VT LVC Link LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE VT tW VT LVC Link CONTROL INPUT tPLZ 0V OUTPUT NORMALLY LOW tPZH 0V SW ITCH CLOSED OUTPUT NORMALLY HIGH ENABLE DISABLE SW ITCH OPEN tPHZ 0V VOL+VLZ VOH VT VT tPZL VLOAD/2 VLOAD/2 VIH VT VOL VOH-VHZ LVC Link TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES SET-UP, HOLD, AND RELEASE TIMES SWITCH POSITION OUTPUT SKEW - tsk (x) DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Symbol VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit VLOAD 66 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF LVC Link Test Switch Open Drain Disable Low Enable Low VLOAD Disable High Enable High GND All Other tests Open LVC Link PULSE WIDTH |
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