IDT74LVC16373APF datasheet(2/6 Pages) IDT

Part #	IDT74LVC16373APF

Description	3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

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Manufacturer	IDT [Integrated Device Technology]

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EXTENDEDCOMMERCIALTEMPERATURERANGE

IDT74LVC16373A

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

1998 Integrated Device Technology, Inc.

DSC-123456

c

PIN CONFIGURATION

SSOP/ TSSOP/ TVSOP

TOP VIEW

CAPACITANCE (TA = +25OC, f = 1.0MHz)

Symbol

Parameter(1)

Conditions

Typ.

Max.

Unit

CIN

Input Capacitance

VIN = 0V

4.5

6

pF

COUT

Output

Capacitance

VOUT = 0V

6.5

8

pF

CI/O

I/O Port

Capacitance

VIN = 0V

6.5

8

pF

LVC Link

NOTE:

1. As applicable to the device type.

1

Q 2

GND

VCC

GND

SO48-1

SO48-2

SO48-3

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

40

41

42

43

44

45

46

47

48

1

Q 1

1

OE

1

Q 4

1

Q 3

1

Q 6

1

Q 5

1

Q 8

1

Q 7

2

Q 1

2

Q 3

2

Q2

2

Q 4

VCC

2

Q 5

2

Q 6

GND

2

Q7

2

Q 8

2

OE

1

D2

GND

VCC

GND

1

D1

1

LE

1

D4

1

D3

1

D6

1

D5

1

D8

1

D7

2

D1

2

D3

2

D2

2

D4

V CC

2

D5

2

D6

GND

2

D7

2

D8

2

LE

ABSOLUTE MAXIMUM RATINGS (1)

Symbol

Description

Max.

Unit

VTERM(2)

Terminal Voltage with Respect to GND

– 0.5 to +6.5

V

VTERM(3)

Terminal Voltage with Respect to GND

– 0.5 to +6.5

V

TSTG

Storage Temperature

– 65 to +150

°C

IOUT

DC Output Current

– 50 to +50

mA

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

– 50

mA

ICC

ISS

Continuous Current through

each VCC or GND

±100

mA

LVC Link

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device.

This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied.

Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. VCC terminals.

3. All terminals except VCC.

PIN DESCRIPTION

Pin Names

Description

xDx

Data Inputs

xLE

Latch Enable Input (Active HIGH)

x

OE

Output Enable Inputs (Active LOW)

xQx

3-State Outputs

FUNCTION TABLE(1)

Inputs

Outputs

xDx

xLE

xOE

xQx

HH

L

H

LHL

L

XL

L

Q

0

XX

HZ

NOTE:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

Q

0 = Output level of Q before the indicated steady-state input

conditions were established.

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