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IDT72V70800 Datasheet(PDF) 14 Page - Integrated Device Technology |
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IDT72V70800 Datasheet(HTML) 14 Page - Integrated Device Technology |
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14 / 21 page  14 COMMERCIALTEMPERATURERANGE IDT72V70800 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 512 x 512 AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK NOTE: 1. High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge CL. Symbol Characteristics Min. Typ. Max. Units tFPW Frame Pulse Width (ST-BUS®, GCI) Bit rate = 8.192 Mb/s 26 80 ns tFPS Frame Pulse Setup time before CLK falling (ST-BUS® or GCI) 5 ns tFPH Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI) 10 ns tCP CLK Period Bit rate = 8.192 Mb/s 55 70 ns tCH CLK Pulse Width HIGH Bit rate = 8.192 Mb/s 20 40 ns tCL CLK Pulse Width LOW Bit rate = 8.192 Mb/s 20 40 ns tr, tf Clock Rise/Fall Time 10 ns tHFPW Wide Frame Pulse Width Bit rate = 8.192 Mb/s 195 295 ns tHFPS Frame Pulse Setup Time before HCLK falling 5 150 ns tHFPH Frame Pulse Hold Time from HCLK falling 10 150 ns tHCP HCLK (4.096 MHz) Period Bit rate = 8.192 Mb/s 190 300 ns tHCH HCLK (4.096 MHz) Pulse Width HIGH Bit rate = 8.192 Mb/s 85 150 ns tHCL HCLK (4.096 MHz) Pulse Width LOW Bit rate = 8.192 Mb/s 85 150 ns tHr,tHf HCLK Rise/Fall Time 10 ns tDIF Delay between falling edge of HCLK and falling edge of CLK -10 10 ns Symbol Characteristics Min. Typ. Max. Unit Test Conditions tSIS RX Setup Time 0 ns tSIH RX Hold Time 10 ns tSOD TX Delay – Active to Active 30 ns C L = 30pF 40 ns C L = 200pF tDZ TX Delay – Active to High-Z 32 ns R L = 1KΩ, CL = 200pF tZD TX Delay – High-Z to Active 32 ns R L = 1KΩ, CL = 200pF tODE Output Driver Enable (ODE) Delay 32 ns R L = 1KΩ, CL = 200pF AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS (1) |
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