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SIO10N268 Datasheet(PDF) 41 Page - SMSC Corporation |
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SIO10N268 Datasheet(HTML) 41 Page - SMSC Corporation |
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41 / 251 page  Advanced Notebook I/O for ISA or LPC Designs Datasheet SMSC SIO10N268 Page 41 Rev. 0.5 (03-24-05) DATASHEET NOTE: If the MEMEN option is not asserted (MEMEN=’0’) the FWHSEL bit is a don’t care and has no effect on the LPC interface. When MEMEN = ‘1’ and the FWHSEL strap option is asserted ‘1’ during VCC POR or Hard Reset, the LPC interface will decode FWH cycles for the X-Bus interface. When the MEMEN=’1’ and the FWHSEL strap option is deasserted ‘0’ during VCC POR or Hard Reset, the LPC interface will decode LPC memory cycles for the X-Bus interface. The affects of the FWHSEL strap option can be overridden by the FWHSEL bit in the FWH ID Select register. The affects of FWHSEL can also be qualified by the IDSELEN and ID SELECT bits in the FWH ID Select register (see section CR54). 8.4.2 FWH and LPC Memory Addressing FWH cycles and LPC memory cycles received on the LPC Bus in the following system memory ranges are forwarded to the X-Bus Interface, if enabled. (see Table 8.5 - FWH Strapping Options) 000E0000h to 000FFFFFh – 128KB Legacy BIOS FF000000h to FFFFFFFFh – 16MB FWH Address Range NOTE: ICH2 only forwards memory reads/writes to the FWH that are in address ranges 000E0000h to 000FFFFFh and FF000000h to FFFFFFFFh. If the FWH or LPC memory address is from 000E0000h to 000FFFFFh, address bits 0 − 19 are forwarded to XA0 – XA19 and nXCS0 is enabled. XA20 is driven to ‘1’ to alias the 128KB legacy system BIOS from the top of 1MB to the top of 4GB system memory. NOTE: At boot-up, all FWH memory cycles will be forwarded to the memory device on chip select 0 (nXCS0 is default) if the MEMEN and FWHSEL strapping options are configured to implement FWH memory transactions. If the FWH or LPC memory address is from FF000000h to FFFFFFFFh, address bits 0 − 20 are forwarded to XA0 − XA20 and nXCS0 is enabled. The Flash device is aligned with the top 2 MB (FFE00000h − FFFFFFFFh) of the 4 GB system memory space. NOTE: The full 16MB address space is mapped to the 2MB X-Bus interface, causing aliasing to FWH memory ranges below FFE00000h. Since no address verification is performed on address bit 21-23, the following 2MB address ranges are aliased or mapped to the X-Bus interface: FFC00000h − FFDFFFFFh, FFA00000h − FFBFFFFFh, FF800000h − FF9FFFFFh, FF600000h − FF7FFFFFh, FF400000h − FF5FFFFFh, FF200000h − FF3FFFFFh, and FF000000h − FF1FFFFFh. 8.4.3 FWH Cycle Types The cycle types supported by the FWH are: FWH Memory Read: 1 byte. FWH Memory Write: 1 byte. |
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