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MC10H644 Datasheet(PDF) 1 Page - ON Semiconductor

Part No. MC10H644
Description  68030/040 PECL-TTL CLOCK DRIVER
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC10H644 Datasheet(HTML) 1 Page - ON Semiconductor

   
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
© Motorola, Inc. 1995
2–1
11/93
REV 3
68030/040
PECL-TTL Clock Driver
The MC10H/100H644 generates the necessary clocks for the 68030,
68040 and similar microprocessors. The device is functionally equivalent
to the H640, but with fewer outputs in a smaller outline 20–lead PLCC
package. It is guaranteed to meet the clock specifications required by the
68030 and 68040 in terms of part–to–part skew, within–part skew and
also duty cycle skew.
Generates Clocks for 68030/040
Meets 68030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and ECL Power/Ground Pins
Within Device Skew on Similar Paths is 0.5 ns
Asynchronous Reset
Single +5.0V Supply
The user has a choice of using either TTL or PECL (ECL referenced to
+5.0V) for the input clock. TTL clocks are typically used in present MPU
systems. However, as clock speeds increase to 50MHz and beyond, the
inherent superiority of ECL (particularly differential ECL) as a means of
clock signal distribution becomes increasingly evident. The H644 also
uses differential ECL internally to achieve its superior skew characteristic.
The H644 includes divide–by–two and divide–by–four stages, both to
achieve the necessary duty cycle and skew to generate MPU clocks as required. A typical 50MHz processor application would
use an input clock running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz (see Logic Symbol).
The 10H version is compatible with MECL 10H
™ ECL logic levels, while the 100H version is compatible with 100K levels
(referenced to +5.0V).
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH.
Synchronized Outputs: The device is designed to have the POS edges of the
÷2 and ÷4 outputs synchronized.
Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT).
The H644 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this
case, the DE side of the input is pulled LOW, and DE goes HIGH.
GT
Q3
GT
Q2
GT
Q4
VT
Q5
GT
R
VE
DE
VBB
DE
GE
Q1
VT
Q0
SEL
DT
19
18
13
17
16
15
14
12
11
10
9
45
67
8
20
1
2
3
Pinout: 20–Lead PLCC (Top View)
MECL 10H is a trademark of Motorola, Inc.
MC10H644
MC100H644
68030/040
PECL–TTL CLOCK
DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 775–02


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