K6T8016C3M-TF55 datasheet(8/9 Pages) SAMSUNG

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K6T8016C3M-TF55 Datasheet(PDF) 8 Page - Samsung semiconductor

Part #	K6T8016C3M-TF55

Description	512Kx16 bit Low Power CMOS Static RAM

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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K6T8016C3M Family

Revision 1.01

April 2000

CMOS SRAM

Address

Data Valid

UB, LB

Data in

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

GND

Data Retention Mode

≥VCC - 0.2V

tSDR

tRDR

tAS(3)

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