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SY88713V Datasheet(PDF) 5 Page - Micrel Semiconductor

Part No. SY88713V
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com

SY88713V Datasheet(HTML) 5 Page - Micrel Semiconductor

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Micrel, Inc.
hbwhelp@micrel.com or (408) 955-1690
The SY88713V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40
°C to +85°C. Signals with data rates up to 622Mbps
and as small as 5mVp-p can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88713V generates
an SD output. SD
LVL sets the sensitivity of the input
amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the SY88713V's
input stage. The high sensitivity of the input amplifier allows
signals as small as 5mVp-p to be detected and amplified.
The input amplifier allows input signals as large as
1800mVp-p. Input signals are linearly amplified with a
typically 38dB differential voltage gain. Since it is a limiting
amplifier, the SY88713V outputs typically 1500mVp-p
voltage-limited waveforms for input signals that are greater
than 18mVp-p. Applications requiring the SY88713V to
operate with high-gain should have the upstream TIA placed
as close as possible to the SY88713V’s input pins to ensure
the best performance of the device.
Output Buffer
The SY88713V’s PECL output buffer is designed to drive
Ω lines. The output buffer requires appropriate termination
for proper operation. An external 50
Ω resistor to V
for each output pin provides this. Figure 3 shows a simplified
schematic of the output stage and includes an appropriate
termination method.
The SY88813V generates a chatter-free PECL signal-
detect (SD) similar to the SY88713V's output buffer. SD is
used to determine that the input amplitude is large enough
to be considered a valid input. SD asserts high if the input
amplitude rises above the threshold set by SD
LVL and
deasserts low otherwise. /EN deasserts the true output signal
without removing the input signals. Typically 4.6dB SD
hysteresis is provided to prevent chattering.
Signal-Detect Level Set
A programmable signal-detect level set pin (SDLVL) sets
the threshold of the input amplitude detection. Setting a
voltage on SDLVL between VCC and VREF sets this threshold.
If desired, a resistor divider between V
CC and VREF, as
shown in Figure 4, also creates this threshold. The smaller
the voltage difference from SD
LVL to VCC, the smaller the
SD sensitivity. Hence, larger input amplitude is required to
assert SD.
“Typical Operating Characteristics” shows the
relationship between the input amplitude detection sensitivity
and the SDLVL voltage.
The SY88713V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2
IN/R for an
electrical signal. Hence the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88713V provides typically 2.3dB
SD optical hysteresis. As the SY88713V is an electrical
device, this datasheet refers to hysteresis in electrical terms.
With 6dB SD hysteresis, a voltage factor of two is required
to assert or deassert SD.

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