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S5D4100X Datasheet(PDF) 26 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
Download  94 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S5D4100X Datasheet(HTML) 26 Page - Samsung semiconductor

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DATASHEET
S5D4100X
26
5.7.2 Output Clock Generation
S5D4100X generates output clock with PLL. Figure 16 shows the structure of PLL.
Receiving the input clock Fin from VCK or X1 pin, the Pre-Divider divides the clock, using the Register PLL_P
value, and send them to PFD. PFD uses the signal received from the Pre-Divider as the reference frequency,
compares the signal with the output of the main divider which is determined by the Register PLL_M value, and
controls the charge pump voltage. VCO generates the output clock, and supplies the final output clock (FOUT) via
Post Scaler1 and Post Scaler2. The signal is divided for lower 2 bits of Register PLL_S for Post Scaler1, and
upper 3 bits of Register PLL_S for Post Scaler2.
The frequency of FOUT is calculated as:
FOUT = Fin * (Pll_M+1) / (PLL_P * 2S)
Where,
S = PLL_S[4:2] + PLL_S[1:0].
Pre-Divider
PFD
Charge
Pump
VCO
Post
Scaler 1
Post
Scaler 2
Main Divider
Fin
FOUT
PLL_P
PLL_M
PLL_S[1:0]
PLL_S[4:2]
23
HS
Figure 16. Structure of Frequency Synthesized PLL


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