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S5D4100X Datasheet(PDF) 25 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
Download  94 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S5D4100X Datasheet(HTML) 25 Page - Samsung semiconductor

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DATASHEET
S5D4100X
25
5.7 TIMING GENERATOR
The timing generator generates the timing used in S5D4100X, and delivers the value required for PCKO (output
clock). Using input HS and VS, the timing generator generates PHSO, PVSO and PDEO for output sync. The
generated timing signals are sent to the internal blocks. TG also delivers the value for generation of PCKO from
MCU to internal PLL.
5.7.1 Output Timing Generation
Using input HS and VS, TG generates the output sync (PHSO, PVSO and PDEN). To set the active data area in
input HS and VS, values for Register HTOTAL, H_STR, HIAS, VTOTAL, V_STR and VIAS are set as shown in
Figure 15. The output signals are defined with the values of Register HOFP, HOSW, HOBP, VOFP, VOSW,
HOAS and VOAS.
HBP
HFP
H_Active
Data_Area
HSW
HTOTAL
H_STR
VBP
VFP
V_Active
Data_Area
VSW
VTOTAL
V_STR
Horizontal
Sync Input
Vertical
Sync Input
HIAS
VIAS
Figure 15. Input Timing


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