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S5D4100X Datasheet(PDF) 22 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
Download  94 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S5D4100X Datasheet(HTML) 22 Page - Samsung semiconductor

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DATASHEET
S5D4100X
22
5.5 INPUT FORMATTER & TEST PAT. GEN.
5.5.1 Input Formatter
The Input Formatter block transforms the input data into the format appropriate for SFC. The block generates
input sync, and adjusts Vsync delay of the odd/even field.
5.5.2 Test Pat. Gen.
The Test Pat. Gen. block generates a pattern for sync and test without input sync and data, and uses it as the
input for SFC. In order to use the test data of the Test Pat. Gen. block, Register TEST_PAT_ON should be HIGH.
In order to use the test sync, Register TP_SYNC_ON should be HIGH.
Figure 11 shows the internally generated sync.
HS
Active Data Area
20
30
VS
Active Line Area
3
16
10
1
Figure 11. Test Sync
The active data area and the active line area are as specified in Registers HIAS and VIAS.
The pattern to be used as the input data for SFC is selected by Register TP_SEL. The image is passed if Bit [7] is
0, and inverted if it is 1. Bit [5] is used to select direction (H/V) of the pattern. Bits [4] ~ [0] are used to select type
of the pattern. The following figure summarizes the above description.
X
[5] [4] [3] [2] [1] [0]
INV.
H/V SEL
0~9 : Type of Pattern
[6]
[7]
not USE
Figure 12. TP_SEL Register


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