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S5D4100X Datasheet(PDF) 54 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
Download  94 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S5D4100X Datasheet(HTML) 54 Page - Samsung semiconductor

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DATASHEET
S5D4100X
54
0x0007
GLOBAL_OUTPUT_CLOCK_AND_SYNC_CONTROL
(Default: 0x 00)
R/W
7:4
CKO_DLY
Output Clock Delay
The register controls delay for the output clock sent to the PCKO pin. The most
significant bit of the 4 bits is the inversion signal.
3
Reserved
2
OPOL_DE
Output Date Enable Signal (PDEO) Polarity
0: HIGH Active
1: LOW Active
1
OPOL_VS
Output VS (PVSO) Polarity
0: LOW Active
1: HIGH Active
0
OPOL_HS
Output HS (PHSO) Polarity
0: LOW Active
1: HIGH Active
0x0008
GLOBAL_CLOCK_AND_SYNC_CONTROL (Default: 0x 04)
R/W
7:4
M2CK_PHASE
Encoder Clock Phase Control
The register controls the clock phase when V601 is 1. It is controlled in the
2MUL block in Figure 7.
3
CKOSC_SEL
CKOSC Clock Select
0: XI Pin
1: The clock selected by ITU656_CH (VCK or VD Pin)
2:0
PDEO_DLY
PDEO Delay
Output Data Enable Signal (PDEO Pin)
0x0009
GLOBAL_GPO (Default: 0x 40)
R/W
7
Reserved
6
CKO_SEL
CKO Domain Clock Select (See Figure 7 Clock System)
0: CKOSC Clock
1: PLL output Clock
5
GPO5
General Purpose Output #5 (See 5.12.4)
4
GPO4
General Purpose Output #4 (See 5.12.4)
3
GPO3
General Purpose Output #3 (See 5.12.4)
2
GPO2
General Purpose Output #2 (See 5.12.4)
1
GPO1
General Purpose Output #1 (See 5.12.4)
0
GPO0
General Purpose Output #0 (See 5.12.4)


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