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S5D4100X Datasheet(PDF) 52 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
Download  94 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S5D4100X Datasheet(HTML) 52 Page - Samsung semiconductor

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DATASHEET
S5D4100X
52
0x0001
GLOBAL_BLOCK_CONTROL2 (Default: 0x 3F)
R/W
7
SIX_WIRE_ON
If HIF Pin is 1, the default value is 3-wire. In order to use Six-Wire,
SIX_WIRE_ON should be set to 1.
0: 3-WIRE MODE
1: 6-WIRE MODE
6
Reserved
5
GBI_ON
Input Domain Clock ON/OFF
0: Input Domain Clock OFF
1: Input Domain Clock ON
4
GBO_ON
Output Domain Clock ON/OFF
0: Output Domain Clock OFF
1: Output Domain Clock ON
3
BU_ON
BOOSTUP Clock ON/OFF
0: BOOSTUP Clock OFF
1: BOOSTUP Clock ON
2
OSD_ON
OSD Clock ON/OFF
0: OSD Clock OFF
1: OSD Clock ON
1
ENC_ON
ENCODER Clock ON/OFF
0: ENCODER Clock OFF
1: ENCODER Clock ON
0
SC_ON
SCALER Clock ON/OFF
0: SCALER Clock OFF
1: SCALER Clock ON
0x0002
GLOBAL_TEST_PATTERN_CONTROL (Default: 0x 3F)
R/W
7
TP_YCbCr_ON
YUV TEST Domain Select
If TP_YUV_ON is 1, TEST_PATTERN is created in the YCbCr domain, and if
TP_YUV_ON is 0, TEST_PATTERN is created in the RGB domain.
0: RGB Domain Select
1: YCbCr Domain Select
6
TP_SYNC_ON
Tests Sync ON
If TEST_PAT_ON and TP_SYNC_ON, the internally created test sync is used
as the input for the scaler. Timing for test sync is described in Figure 11.
0: Test Sync OFF
1: Test Sync ON
5:0
TP_RGB_ON
Test pattern RGB ON/OFF Register
2 bits are assigned and controlled for RGB respectively.
[5:4] - R , [3:2] - G , [1:0] – B
See Table 5.1 for description on the 2 bits.
If TP_YCbCr_ON is 1, YCbCr is controlled instead of RGB.


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