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S5D4100X Datasheet(PDF) 5 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
Download  94 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S5D4100X Datasheet(HTML) 5 Page - Samsung semiconductor

 
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Figure of Contents
Figure 1
80-TQFP-1212 ..............................................................................................................9
Figure 2
88-FBGA-0707 (PAD Domain) ...................................................................................10
Figure 3
88-FBGA-0707............................................................................................................12
Figure 4
Functional Block Diagram ...........................................................................................15
Figure 5
Solution Circuit for Application (TQFP).......................................................................16
Figure 6
Solution Circuit for Application (FBGA).......................................................................17
Figure 7
Clock Systems ...........................................................................................................18
Figure 8
ITU Decoder ...............................................................................................................19
Figure 9
Adaptive Brightness Control LUT ...............................................................................20
Figure 10
Sharpness I/O Characteristic Curve ...........................................................................21
Figure 11
Test Sync ...................................................................................................................22
Figure 12
TP_SEL Register ........................................................................................................22
Figure 13
Types of Pattern..........................................................................................................23
Figure 14
Pattern 6 (Constant Level) ..........................................................................................23
Figure 15
Input Timing ................................................................................................................25
Figure 16
Structure of Frequency Synthesized PLL ...................................................................26
Figure 17
OSD Font Structure ....................................................................................................27
Figure 18
OSD DISPLAY RAM Structure ...................................................................................28
Figure 19
OSD Position .............................................................................................................29
Figure 20
Board/Shadow ...........................................................................................................30
Figure 21
Creating Border When There is No Space on the Right ............................................31
Figure 22
When There is no Space on the Left ..........................................................................32
Figure 23
Creating Border on the Left Space .............................................................................32
Figure 24
OSD Multicolor Font Structure....................................................................................34
Figure 25
OSD Region Definition................................................................................................35
Figure 26
OSD RAM Structure....................................................................................................36
Figure 27
OSD Font Structure ....................................................................................................37
Figure 28
OSD Font RAM & Display RAM Structure ..................................................................38
Figure 29
OSD System Block Diagram.......................................................................................39
Figure 30
Gamma Graph ...........................................................................................................40
Figure 31
6-wire Host Interface Write Data Sequence (Sending n data) ...................................41
Figure 32
6-wire Host Interface Read Data Sequence (Reading n data) ...................................42
Figure 33
I2C Host Interface Write Data Sequence ...................................................................43
Figure 34
I2C Host Interface Read Data Sequence ...................................................................43
Figure 35
3-wire Host Interface Write Data Sequence ...............................................................45
Figure 36
3-wire Host Interface Read Data Sequence ...............................................................45
Figure 37
PWM ...........................................................................................................................46
Figure 38
Parallel interface Panel Architecture...........................................................................47
Figure 39
Parallel Output Data....................................................................................................47
Figure 40
Delta Type Panel Architecture ....................................................................................48
Figure 41
Serial Output Data ......................................................................................................48


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