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S5D4100X Datasheet(PDF) 45 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
Download  94 Pages
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S5D4100X Datasheet(HTML) 45 Page - Samsung semiconductor

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DATASHEET
S5D4100X
45
5.12.3 3-wire Host Interface Protocol
S5D4100X supports data communication based on 3-WIRE Host Interface Protocol. The address used is 15 bits,
and the data depth is 8 bits. 3-WIRE is active in the section where the SCSN line is LOW. The upper 1 bit of the
initial 16 bits indicates R/W (R: HIGH, W: LOW), and the remaining 15 bits indicate the address. The write (or
read) data are after the address and before stop. In case of address or write data, the master (MCU) should send
the data at the SCL rising edge, and the slave (S5D4100X) should receive the data at the SCL falling edge. On
the contrary, for read data, the slave sends the data at the SCL falling edge, and the master receives the data at
the SCL rising edge.
Remark
MS: MASTER Send to SLAVE
MR: MASTER Receive
SS: SLAVE Send to MASTER
SR: SLAVE Receive
15 bits Address
8 bits Data
Start
Stop
ADDRESS
DATA
W
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
SCSN
SCL
SDA
Figure 35. 3-wire Host Interface Write Data Sequence
15 bits Address
8 bits Data
Start
Stop
ADDRESS
DATA
R
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
SR
SS
MR
SS
MR
SS
MR
SS
MR
SS
MR
SS
MR
SS
MR
SS
MR
SS
MR
SCSN
SCL
SDA
Figure 36. 3-wire Host Interface Read Data Sequence


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