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S5D4100X Datasheet(PDF) 43 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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S5D4100X Datasheet(HTML) 43 Page - Samsung semiconductor

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DATASHEET
S5D4100X
43
5.12.2 I2C Host Interface Protocol
S5D4100X supports data communication based on I2C Protocol. The slave address which corresponds to the
device ID is 7 bits (binary “0000101”). The address used is 15 bits, and the data depth is 8 bits. Therefore, in
order to access an address, the product indexes 2 bytes (Address MSB, Address LSB), and uses the 1-byte data
depth. Since the address bits are 15 bits, the 1 byte for address MSB is “X A14 A13 A12 A11A10 A9 A8”, and the 1
byte for address LSB is Binary “A7 A6 A5 A4 A3 A2 A1 A0”.
1) Timing Chart (Data sequence in write/read of n registers)
W
Start
ACK
ACK
SDA
SCL
Device ID
Address MSB
ACK
ACK
SDA
SCL
Address LSB
Data 1
Stop
SDA
SCL
Data 2
Data n
ACK
Figure 33. I2C Host Interface Write Data Sequence
R
Start
ACK
ACK
SDA
SCL
Device ID
Address MSB
ACK
ACK
SDA
SCL
Address LSB
Data 1
Stop
ACK
SDA
SCL
Data 2
Data n
Figure 34. I2C Host Interface Read Data Sequence
In the above timing chart, the device ID (slave address) and read/write byte are as follows.


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