Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

S5D4100X Datasheet(PDF) 41 Page - Samsung semiconductor

Part No. S5D4100X
Description  Digital Interface Including Scaler, Image Enhancement
Download  94 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
Logo 

S5D4100X Datasheet(HTML) 41 Page - Samsung semiconductor

Zoom Inzoom in Zoom Outzoom out
 41 / 94 page
background image
DATASHEET
S5D4100X
41
5.12 HOST INTERFACE
The host interface supports 3 protocols (6-Wire Host Interface Protocol, 3-Wire Host Interface Protocol and I2C
Host Interface Protocol), and also supports the supplementary functions PWM and GPO. In order to use I2C Host
Interface Protocol, HIF pin should be set to HIGH, and in order to use 3-Wire Host Interface Protocol, HIF pin
should be set to LOW. To select 6-Wire Host Interface, as HIF = LOW, Register SIX_WIRE_ON should be set to
HIGH.
5.12.1 6-wire Host Interface Protocol
S5D4100X supports data communication based on 6-WIRE Host Interface Protocol. The address used is 15 bits,
and the data depth is 8 bits. 6-WIRE is active in the section where the SCSN line is LOW. The upper 1-bit of the
initial 16 bits indicates R/W (R: HIGH, W: LOW), and the remaining 15 bits indicate the address. The write (or
read) data are after the address and before stop. In case of address or write data, the master (MCU) should send
the data at the SCL rising edge, and the slave (S5D4100X) should receive the data at the SCL falling edge. On
the contrary, for read data, the slave sends the data at the SCL falling edge, and the master receives the data at
the SCL rising edge.
Timing Chart (Data sequence in write/read of n registers)
Remark
MS: MASTER Send to SLAVE
MR: MASTER Receive
SS: SLAVE Send to MASTER
SR: SLAVE Receive
W
Start
Stop
SCL
MS
SCSN
ADDR[11]
ADDR[7]
ADDR[3]
DATA1[7]
DATA1[3]
DATA2[7]
DATAn[3]
SDA3
ADDR[10]
ADDR[6]
ADDR[2]
DATA1[6]
DATA1[2]
DATA2[6]
DATAn[2]
SDA2
ADDR[14]
ADDR[9]
ADDR[5]
ADDR[1]
DATA1[5]
DATA1[1]
DATA2[5]
DATAn[1]
SDA1
ADDR[13]
ADDR[8]
ADDR[4]
ADDR[0]
DATA1[4]
DATA1[0]
DATA2[4]
DATAn[0]
SDA0
ADDR[12]
SR
MS
SR
MS
SR
MS
SR
MS
SR
MS
MS
SR
SR
SR
Figure 31. 6-wire Host Interface Write Data Sequence (Sending n data)


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn