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CY241V08A-05 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. CY241V08A-05
Description  MPEG Clock Generator with VCXO
Download  6 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY241V08A-05 Datasheet(HTML) 1 Page - Cypress Semiconductor

   
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MPEG Clock Generator with VCXO
CY241V08A-05,06
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-07670 Rev. **
Revised April 09, 2004
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
• Compatible with MK3727 (–5, –6)
• Application compatibility for a wide variety of designs
• Enables design compatibility
• Lower drive strength settings (CY241V08A–06)
Benefits
• Digital VCXO control
• Electromagnetic interference (EMI) reduction for standards
compliance
• Second source for existing designs
• Highest-performance PLL tailored for multimedia applica-
tions
• Meets critical timing requirements in complex system
designs
Part
Number
Outputs
Input Frequency Range
Output
Frequencies
VCXO Control
Curve
Other Features
CY241V08A–05
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz non-linear
Compatible with
MK3727A non linear
VCXO control
CY241V08A–06
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz non-linear
Same as CY241V08A–05
except lower drive
strength
CY241V08A–05,–06 Logic Block Diagram
13.5 XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
VCXO
Q
P
VCO
VDD
VSS
Φ
27 MHz
8-pin SOIC
CY241V08A–05,–06
1
2
3
4
XOUT
XIN
VCXO
27 MHz
VSS
NC or VSS
NC or VDD
5
6
7
8
VDD
Pin Configurations


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