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CY241V08A-05 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. CY241V08A-05
Description  MPEG Clock Generator with VCXO
Download  6 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY241V08A-05 Datasheet(HTML) 4 Page - Cypress Semiconductor

   
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CY241V08A-05,06
Document #: 38-07670 Rev. **
Page 4 of 6
Voltage and Timing Definitions
Note:
3. Not 100% tested.
AC Electrical Specifications (VDD = 3.3V) [3]
Parameter[3]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
45
50
55
%
EROR
Rising Edge Rate –05
Output Clock Edge Rate, Measured from 20%
to 80% of VDD, CLOAD = 15 pF See Figure 2.
0.8
1.4
V/ns
EROF
Falling Edge Rate –05
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15 pF See Figure 2.
0.8
1.4
V/ns
EROR
Rising Edge Rate –06
Output Clock Edge Rate, Measured from 20%
to 80% of VDD, CLOAD = 15 pF See Figure 2.
0.7
1.1
V/ns
EROF
Falling Edge Rate –06
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15 pF See Figure 2.
0.7
1.1
V/ns
t9
Clock Jitter
Peak-to-peak period jitter
100
ps
t10
PLL Lock Time
3
ms
Test and Measurement Set-up
0.1
µF
VDD
Outputs
CLOAD
GND
DUT
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Figure 1. Duty Cycle Definition
Clock
Output
t
3
t
4
V
DD
80% of V
DD
20% of V
DD
0V
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4


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