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SI3024 Datasheet(PDF) 43 Page - List of Unclassifed Manufacturers

Part # SI3024
Description  GLOBAL MC 97 SILICON DAA
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SI3024 Datasheet(HTML) 43 Page - List of Unclassifed Manufacturers

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Si3038
Rev. 2.01
43
Reset setting for Line 1 device = 0x0000
Reset setting for Line 2 device = 0x8080
This read/write register controls the modem AFE DAC and ADC levels. The default value after cold register reset
for this register (0x8080) corresponds to 0 db DAC attenuation with mute on and 0 db ADC gain with mute on.
Reset setting for Line 1 device = 0x003F
Reset setting for Line 2 device = 0xFC00
The GPIO Pin Configuration register is read/write for configuring Slot 12 I/O. These pins are digital commands
(virtual pins). This register specifies whether a GPIO pin is configured for input (1) or output (0). The digital
controller sends the desired GPIO pin value over output slot 12 in the outgoing stream of the AC-link before
configuring any of these bits for output.
Register 48h Line 2 DAC/ADC Level
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Mute
DAC3 DAC2 DAC1
Mute
ADC3 ADC2 ADC1
Bit
Name
Function
15
Mute
Transmit Mute.
0 = mute off.
1 = mute on.
14:12
Reserved Read returns zero.
11:9
DAC[3:1]
Analog Transmit Attenuation.
000 = 0 db attenuation.
001 = 3 db attenuation.
010 = 6 db attenuation.
011 = 9 db attenuation.
1xx = 12 db attenuation.
8
Reserved Read returns zero.
7Mute
Receive Mute.
0 = mute off.
1 = mute on.
6:4
Reserved Read returns zero.
3:1
ADC[3:1]
Analog Receive Gain.
000 = 0 db gain.
001 = 3 db gain.
010 = 6 db gain.
011 = 9 db gain.
1xx = 12 db gain.
0
Reserved Read returns zero.
Register 4Ch GPIO Pin Configuration
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GC15 GC14 GC13 GC12 GC11 GC10
GC5
GC4
GC3
GC2
GC1
GC0


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