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EDS2532EEBH-75 Datasheet(PDF) 39 Page - Elpida Memory

Part No. EDS2532EEBH-75
Description  256M bits SDRAM (8M words x 32 bits)
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Maker  ELPIDA [Elpida Memory]
Homepage  http://www.elpida.com/en
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EDS2532EEBH-75 Datasheet(HTML) 39 Page - Elpida Memory

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EDS2532EEBH-75
Preliminary Data Sheet E0639E50 (Ver. 5.0)
39
DQM Control
The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively.
The timing of UDQM/LDQM is different during reading and writing.
Reading
When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes
Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding
data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks.
Writing
Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to
High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0
clock.
CLK
DQ
out 0
out 1
lDOD = 2 Latency
out 3
DQM
High-Z
Reading
CLK
DQ
in 0
in 1
lDID = 0 Latency
in 3
DQM
Writing


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