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EDS2532EEBH-75 Datasheet(PDF) 33 Page - Elpida Memory

Part No. EDS2532EEBH-75
Description  256M bits SDRAM (8M words x 32 bits)
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Maker  ELPIDA [Elpida Memory]
Homepage  http://www.elpida.com/en
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EDS2532EEBH-75 Datasheet(HTML) 33 Page - Elpida Memory

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EDS2532EEBH-75
Preliminary Data Sheet E0639E50 (Ver. 5.0)
33
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
CLK
Command
DQ (input)
WRIT
READ
in A0
out B1
out B2
out B3
out B0
DQ (output)
Column = A
Write
Column = B
Read
Column = B
Dout
/CAS Latency
DQM
Burst Write Mode
CL = 2
BL = 4
Bank 0
WRITE to READ Command Interval (1)
CLK
Command
DQ (input)
WRIT
READ
in A0
out B1
out B2
out B3
out B0
DQ (output)
Column = A
Write
Column = B
Read
Column = B
Dout
/CAS Latency
in A1
DQM
Burst Write Mode
CL = 2
BL = 4
Bank 0
WRITE to READ Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank and
the same address).


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