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EDS2532EEBH-75 Datasheet(PDF) 32 Page - Elpida Memory

Part No. EDS2532EEBH-75
Description  256M bits SDRAM (8M words x 32 bits)
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Maker  ELPIDA [Elpida Memory]
Homepage  http://www.elpida.com/en
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EDS2532EEBH-75 Datasheet(HTML) 32 Page - Elpida Memory

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EDS2532EEBH-75
Preliminary Data Sheet E0639E50 (Ver. 5.0)
32
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
DQ (output)
in B2
in B3
READ
WRIT
in B0
in B1
High-Z
DQ (input)
CL=2
CL=3
DQM
BL = 4
Burst write
READ to WRITE Command Interval (1)
CLK
Command
DQ
READ
WRIT
CL=2
CL=3
DQM
2 clock
out
out
out
out
out
in
in
in
in
in
in
in
in
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the
output buffer becomes High-Z before data input.


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