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EDS1232AATA-75L-E Datasheet(PDF) 29 Page - Elpida Memory

Part # EDS1232AATA-75L-E
Description  128M bits SDRAM (4M words x 32 bits)
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDS1232AATA-75L-E Datasheet(HTML) 29 Page - Elpida Memory

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EDS1232AATA
Data Sheet E0386E40 (Ver. 4.0)
29
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
CLK
lAPR
lRAS
lAPR
CL=2 Command
CL=3 Command
DQ
DQ
Note: Internal auto-precharge starts at the timing indicated by "
".
And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge "
".
ACT
READA
ACT
out3
out2
out1
out0
lRAS
ACT
READA
ACT
out3
out2
out1
out0
Burst Read (BL = 4)
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
CLK
Command
DQ
lDAL
lRAS
ACT
WRITA
in0
in1
in2
in3
ACT
Note: Internal auto-precharge starts at the timing indicated by "
".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge "
".
Burst Write (BL = 4)


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