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EDD2508AKTA-5 Datasheet(PDF) 36 Page - Elpida Memory

Part No. EDD2508AKTA-5
Description  256M bits DDR SDRAM (32M words x 8 bits, DDR400)
Download  48 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDD2508AKTA-5 Datasheet(HTML) 36 Page - Elpida Memory

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EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
36
A Write command to the consecutive Precharge command interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
in0
in1
in2
in3
CK
/CK
DQ
DM
DQS
Command
t1
t0
t2
t3
t4
t5
t6
t7
Last data input
tWPD
;
;
;
;;
WRIT
NOP
tWR
PRE/PALL
NOP
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
Precharge Termination in Write Cycles
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command
of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command
is issued, the invalid data must be masked by DM.
in2
in3
;
;
in0
in1
CK
/CK
DQ
DM
DQS
Command
t1
t0
t2
t3
t4
t5
t6
t7
Data masked
;
;
;
;;
WRIT
NOP
NOP
tWR
PRE/PALL
Precharge Termination in Write Cycles (same bank) (BL = 4)


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