Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

EDD2508AKTA-5 Datasheet(PDF) 33 Page - Elpida Memory

Part No. EDD2508AKTA-5
Description  256M bits DDR SDRAM (32M words x 8 bits, DDR400)
Download  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDD2508AKTA-5 Datasheet(HTML) 33 Page - Elpida Memory

Back Button EDD2508AKTA-5 Datasheet HTML 29Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 30Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 31Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 32Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 33Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 34Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 35Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 36Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 37Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 33 / 48 page
background image
EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
33
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read
command
Bank
address
Row address State
Operation
1. Same
Same
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
2. Same
Different
—*
1
3. Different
Any
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
IDLE
—*
1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
in0
in1
in2
out0 out1 out2 out3
CK
/CK
DM
DQ
Command
t1
t0
t2
t3
t4
t5
t6
t7
t8
BL = 4
CL = 3
DQS
Data masked
1 cycle
READ
NOP
WRIT
High-Z
High-Z
CL=3
[WRITE to READ delay = 1 clock cycle]


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn