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EDD2508AKTA-5 Datasheet(PDF) 27 Page - Elpida Memory

Part No. EDD2508AKTA-5
Description  256M bits DDR SDRAM (32M words x 8 bits, DDR400)
Download  48 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDD2508AKTA-5 Datasheet(HTML) 27 Page - Elpida Memory

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EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
27
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the
consecutive read command
Bank
address
Row address State
Operation
1. Same
Same
ACTIVE
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
2. Same
Different
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
3. Different
Any
ACTIVE
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
IDLE
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
out
A0
out
A1
out
B0
out
B1
out
B2
out
B3
CK
/CK
Address
BA
DQ
DQS
Command
t0
t4
t5
t6
t7
t8
t9
t10
Bank0
Active
CL = 3
BL = 4
Bank0
NOP
ACT
NOP
READ
Row
Column A
READ
Column B
Column = A
Read
Column = B
Read
Column = A
Dout
Column = B
Dout
t11
READ to READ Command Interval (same ROW address in the same bank)


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