Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

EDD2508AKTA-5 Datasheet(PDF) 23 Page - Elpida Memory

Part No. EDD2508AKTA-5
Description  256M bits DDR SDRAM (32M words x 8 bits, DDR400)
Download  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDD2508AKTA-5 Datasheet(HTML) 23 Page - Elpida Memory

Back Button EDD2508AKTA-5 Datasheet HTML 19Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 20Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 21Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 22Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 23Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 24Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 25Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 26Page - Elpida Memory EDD2508AKTA-5 Datasheet HTML 27Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 23 / 48 page
background image
EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
23
Read/Write Operations
Bank active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select
address which are loaded via the A0 to A12 and BA0, BA1 pins in the cycle when the read command is issued. The
data output timing are characterized by CL and tAC. The read burst start CL
• tCK + tAC (ns) after the clock rising
edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously
with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low
period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling
edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed.
tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is
referred as read postamble.
out0 out1
out0 out1 out2 out3
out0 out1 out2 out3 out4 out5 out6 out7
CK
/CK
Address
DQS
DQ
BL = 2
BL = 4
BL = 8
Command
CL = 3
BL: Burst length
t1
t0
t5
t6
t7
t8
t9
t10
tRCD
tRPRE
tRPST
ACT
NOP
NOP
NOP
READ
Row
Column
t11
Read Operation (Burst Length)


Similar Part No. - EDD2508AKTA-5

ManufacturerPart No.DatasheetDescription
Elpida Memory
Elpida Memory
EDD2508AKTA-5-E ELPIDA-EDD2508AKTA-5-E Datasheet
551Kb / 48P
   256M bits DDR SDRAM (32M words x 8 bits, DDR400)
EDD2508AKTA-5B-E ELPIDA-EDD2508AKTA-5B-E Datasheet
551Kb / 48P
   256M bits DDR SDRAM (32M words x 8 bits, DDR400)
EDD2508AKTA-5C-E ELPIDA-EDD2508AKTA-5C-E Datasheet
551Kb / 48P
   256M bits DDR SDRAM (32M words x 8 bits, DDR400)
More results

Similar Description - EDD2508AKTA-5

ManufacturerPart No.DatasheetDescription
Elpida Memory
Elpida Memory
EDD2508AKTA-5-E ELPIDA-EDD2508AKTA-5-E Datasheet
551Kb / 48P
   256M bits DDR SDRAM (32M words x 8 bits, DDR400)
EDD2516AKTA-5-E ELPIDA-EDD2516AKTA-5-E Datasheet
558Kb / 48P
   256M bits DDR SDRAM (16M words x16 bits, DDR400)
EDD2516AKTA-E ELPIDA-EDD2516AKTA-E Datasheet
564Kb / 49P
   256M bits DDR SDRAM (16M words x 16 bits)
EDD2504AKTA-E ELPIDA-EDD2504AKTA-E Datasheet
555Kb / 49P
   256M bits DDR SDRAM (64M words x 4 bits)
EDD1216AATA-5 ELPIDA-EDD1216AATA-5 Datasheet
556Kb / 48P
   128M bits DDR SDRAM (8M words x 16 bits, DDR400)
EDD2504AKTA ELPIDA-EDD2504AKTA Datasheet
441Kb / 49P
   256M bits DDR SDRAM (64M words x 4 bits)
EDD2516KCTA-SI ELPIDA-EDD2516KCTA-SI Datasheet
579Kb / 52P
   256M bits DDR SDRAM 256M bits DDR SDRAM
EDS2516ADTA-75 ELPIDA-EDS2516ADTA-75 Datasheet
702Kb / 50P
   256M bits SDRAM (16M words x 16 bits)
EDS2532EEBH-9A ELPIDA-EDS2532EEBH-9A Datasheet
718Kb / 50P
   256M bits SDRAM (8M words x 32 bits)
EDS2532EEBH-75 ELPIDA-EDS2532EEBH-75 Datasheet
718Kb / 50P
   256M bits SDRAM (8M words x 32 bits)
More results


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48 


Datasheet Download

Go To PDF Page


Link URL



Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz