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EDD1216AATA Datasheet(PDF) 17 Page - Elpida Memory |
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EDD1216AATA Datasheet(HTML) 17 Page - Elpida Memory |
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17 / 49 page  EDD1216AATA Data Sheet E0444E40 (Ver. 4.0) 17 Current state /CS /RAS /CAS /WE Address Command Operation Next state Write with auto- pre-charge* 10 H × × × × DESL NOP Precharging L H H H × NOP NOP Precharging L H H L × BST ILLEGAL — L H L H BA, CA, A10 READ/READA ILLEGAL* 14 — L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL* 14 — L L H H BA, RA ACT ILLEGAL* 11, 14 — L L H L BA, A10 PRE, PALL ILLEGAL* 11, 14 — L L L × × ILLEGAL — Remark: H: VIH. L: VIL. ×: VIH or VIL Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. 2. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued. 3. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued. 4. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued. 5. The DDR SDRAM is in "Active" state after "Activating" is completed. 6. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been output and DQ output circuits are turned off. 8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input. 9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input. 10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input. 11. This command may be issued for other banks, depending on the state of the banks. 12. All banks must be in "IDLE". 13. Before executing a write command to stop the preceding burst read operation, BST command must be issued. 14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.) The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below. From command To command (different bank, non- interrupting command) Minimum delay (Concurrent AP supported) Units Read w/AP Read or Read w/AP BL/2 tCK Write or Write w/AP CL(rounded up)+ (BL/2) tCK Precharge or Activate 1 tCK Write w/AP Read or Read w/AP 1 + (BL/2) + tWTR tCK Write or Write w/AP BL/2 tCK Precharge or Activate 1 tCK |
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