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EBE51ED8AEFA-6 Datasheet(PDF) 16 Page - Elpida Memory |
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EBE51ED8AEFA-6 Datasheet(HTML) 16 Page - Elpida Memory |
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16 / 22 page  EBE51ED8AEFA-6 Data Sheet E0724E10 (Ver. 1.0) 16 -6E Frequency (Mbps) 667 Parameter Symbol min. max. Unit Notes Read preamble tRPRE 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 tCK Active to precharge command tRAS 45 70000 ns Active to auto-precharge delay tRAP tRCD min. ns Active bank A to active bank B command period tRRD 7.5 ns Write recovery time tWR 15 ns Auto precharge write recovery + precharge time tDAL (tWR/tCK)+ (tRP/tCK) tCK 1 Internal write to read command delay tWTR 7.5 ns Internal read to precharge command delay tRTP 7.5 ns Exit self refresh to a non-read command tXSNR tRFC + 10 ns Exit self refresh to a read command tXSRD 200 tCK Exit precharge power down to any non-read command tXP 2 tCK Exit active power down to read command tXARD 2 tCK 3 Exit active power down to read command (slow exit/low power mode) tXARDS 7 − AL tCK 2, 3 CKE minimum pulse width (high and low pulse width) tCKE 3 tCK Output impedance test driver delay tOIT 0 12 ns Auto refresh to active/auto refresh command time tRFC 105 ns Average periodic refresh interval (0 °C ≤ TC ≤ +85°C) tREFI 7.8 µs (+85 °C < TC ≤ +95°C) tREFI 3.9 µs Minimum time clocks remains ON after CKE asynchronously drops low tDELAY tIS + tCK + tIH ns Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer. 2. AL: Additive Latency. 3. MRS A12 bit defines which active power down exit timing to be applied. 4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test. DQS /DQS tDS tDH tDS tDH VDDQ VIH (AC)(min.) VIH (DC)(min.) VIL (DC)(max.) VIL (AC)(max.) VSS VREF CK /CK tIS tIH tIS tIH VDDQ VIH (AC)(min.) VIH (DC)(min.) VIL (DC)(max.) VIL (AC)(max.) VSS VREF Input Waveform Timing 1 (tDS, tDH) Input Waveform Timing 2 (tIS, tIH) |
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