EBE51ED8AEFA-6 datasheet(11/22 Pages) ELPIDA | 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)

Part No.	EBE51ED8AEFA-6

Description	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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EBE51ED8AEFA-6

Data Sheet E0724E10 (Ver. 1.0)

11

DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)

Parameter

Symbol

Grade

max.

Unit

Test condition

Operating current

(ACT-PRE)

IDD0

1035

mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(ACT-READ-PRE)

IDD1

1170

mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Precharge power-down

standby current

IDD2P

90

mA

all banks idle;

tCK = tCK (IDD);

CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Precharge quiet standby

current

IDD2Q

225

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Idle standby current

IDD2N

315

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD3P-F

360

mA

Fast PDN Exit

MRS(12) = 0

Active power-down

standby current

IDD3P-S

225

mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and address bus

inputs are STABLE;

Data bus inputs are FLOATING

Slow PDN Exit

MRS(12) = 1

Active standby current

IDD3N

630

mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(Burst read operating)

IDD4R

2070

mA

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

(Burst write operating)

IDD4W

1980

mA

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Auto-refresh current

IDD5

2430

mA

tCK = tCK (IDD);

Refresh command at every tRFC (IDD) interval;

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

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