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EBE51ED8ABFA Datasheet(PDF) 17 Page - Elpida Memory

Part No. EBE51ED8ABFA
Description  512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBE51ED8ABFA Datasheet(HTML) 17 Page - Elpida Memory

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EBE51ED8ABFA
Data Sheet E0378E40 (Ver. 4.0)
17
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter
Symbol
min.
max.
Unit
Notes
ODT turn-on delay
tAOND
2
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)
+ 1000
ps
1
ODT turn-on (power down mode)
tAONPD
tAC(min)
+ 2000
2tCK
+ tAC(max) + 1000
ps
ODT turn-off delay
tAOFD
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)
+ 600
ps
2
ODT turn-off (power down mode)
tAOFPD
tAC(min)
+ 2000
2.5tCK
+ tAC(max) + 1000
ps
ODT to power down entry latency
tANPD
3
3
tCK
ODT power down exit latency
tAXPD
8
8
tCK
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
2. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
AC Input Test Conditions
Parameter
Symbol
Value
Unit
Notes
Input reference voltage
VREF
0.5
× VDDQ
V
1
Input signal maximum peak to peak swing
VSWING(max.)
1.0
V
1
Input signal maximum slew rate
SLEW
1.0
V/ns
2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the
device under test.
2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC)
(min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in
the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive
transitions and VIH(AC) to VIL(AC) on the negative transitions.
VSWING(max.)
∆TR
∆TF
Start of falling edge input timing
Start of rising edge input timing
VIH (DC)(min.)
VIL (AC)(max.)
∆TF
Falling slew =
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VREF
VIH (AC) min.
VIL (DC)(max.)
∆TR
Rising slew =
AC Input Test Signal Wave forms
VTT
Measurement point
DQ
RT =25
Output Load


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