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EBE20RE4AAFA Datasheet(PDF) 1 Page - Elpida Memory

Part No. EBE20RE4AAFA
Description  2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBE20RE4AAFA Datasheet(HTML) 1 Page - Elpida Memory

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Document No. E0440E30 (Ver. 3.0)
Date Published March 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005
DATA SHEET
2GB Registered DDR2 SDRAM DIMM
EBE20RE4AAFA (256M words
× 72 bits, 1 Rank)
Description
The EBE20RE4AAFA is a 256M words
× 72 bits, 1
rank DDR2 SDRAM Module, mounting 18 pieces of
DDR2 SDRAM sealed in FBGA (
µBGA) package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 4bits prefetch-pipelined
architecture.
Data strobe (DQS and /DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA
(
µBGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
• 240-pin socket type dual in line memory module
(DIMM)
 PCB height: 30.0mm
 Lead pitch: 1.0mm
 Lead-free
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 533Mbps/400Mbps (max.)
• SSTL_18 compatible I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Eight internal banks for concurrent operation
(Component)
• Burst length: 4, 8
• /CAS latency (CL): 3, 4, 5
• Auto precharge option for each burst access
• Auto refresh and self refresh modes
• Average refresh period
 7.8µs at 0°C ≤ TC ≤ +85°C
 3.9µs at +85°C < TC ≤ +95°C
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)


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