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EBD51RC4AKFA-E Datasheet(PDF) 6 Page - Elpida Memory |
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EBD51RC4AKFA-E Datasheet(HTML) 6 Page - Elpida Memory |
6 / 19 page ![]() EBD51RC4AKFA-E Data Sheet E0608E10 (Ver. 1.0) 6 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 28 Minimum row active to row active delay (tRRD) -6B 0 0 1 1 0 0 0 0 30H 12ns -7A, -7B 0 0 1 1 1 1 0 0 3CH 15ns 29 Minimum /RAS to /CAS delay (tRCD) -6B 0 1 0 0 1 0 0 0 48H 18ns -7A, -7B 0 1 0 1 0 0 0 0 50H 20ns 30 Minimum active to precharge time (tRAS) -6B 0 0 1 0 1 0 1 0 2AH 42ns -7A, -7B 0 0 1 0 1 1 0 1 2DH 45ns 31 Module rank density 1 0 0 0 0 0 0 0 80H 1 rank 512MB 32 Address and command setup time before clock (tIS) -6B 0 1 1 1 0 1 0 1 75H 0.75ns* 3 -7A, -7B 1 0 0 1 0 0 0 0 90H 0.9ns* 3 33 Address and command hold time after clock (tIH) -6B 0 1 1 1 0 1 0 1 75H 0.75ns* 3 -7A, -7B 1 0 0 1 0 0 0 0 90H 0.9ns* 3 34 Data input setup time before clock (tDS) -6B 0 1 0 0 0 1 0 1 45H 0.45ns* 3 -7A, -7B 0 1 0 1 0 0 0 0 50H 0.5ns* 3 35 Data input hold time after clock (tDH) -6B 0 1 0 0 0 1 0 1 45H 0.45ns* 3 -7A, -7B 0 1 0 1 0 0 0 0 50H 0.5ns* 3 36 to 40 Superset information 0 0 0 0 0 0 0 0 00H Future use 41 Active command period (tRC) -6B 0 0 1 1 1 1 0 0 3CH 60ns* 3 -7A, -7B 0 1 0 0 0 0 0 1 41H 65ns* 3 42 Auto refresh to active/ Auto refresh command cycle (tRFC) -6B 0 1 0 0 1 0 0 0 48H 72ns* 3 -7A, -7B 0 1 0 0 1 0 1 1 4BH 75ns* 3 43 SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30H 12ns* 3 44 Dout to DQS skew -6B 0 0 1 0 1 1 0 1 2DH 0.45ns* 3 -7A, -7B 0 0 1 1 0 0 1 0 32H 0.5ns* 3 45 Data hold skew (tQHS) -6B 0 1 0 1 0 1 0 1 55H 0.55ns* 3 -7A, -7B 0 1 1 1 0 1 0 1 75H 0.75ns* 3 46 to 61 Superset information 0 0 0 0 0 0 0 0 00H Future use 62 SPD revision 0 0 0 0 0 0 0 0 00H Initial 63 Checksum for bytes 0 to 62 -6B 0 1 0 1 0 0 0 1 51H 81 -7A 0 0 0 0 1 0 0 0 08H 8 -7B 0 0 1 1 0 0 1 1 33H 51 64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH Continuation code 66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory |