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EBD51RC4AKFA Datasheet(PDF) 5 Page - Elpida Memory

Part No. EBD51RC4AKFA
Description  512MB Registered DDR SDRAM DIMM (64M words X 72 bits, 1 Rank)
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBD51RC4AKFA Datasheet(HTML) 5 Page - Elpida Memory

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EBD51RC4AKFA
Data Sheet E0377E20 (Ver. 2.0)
5
Serial PD Matrix*
1
Byte No.
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
128
1
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
256 byte
2
Memory type
0
0
0
0
0
1
1
1
07H
SDRAM DDR
3
Number of row address
0
0
0
0
1
1
0
1
0DH
13
4
Number of column address
0
0
0
0
1
0
1
1
0BH
11
5
Number of DIMM ranks
0
0
0
0
0
0
0
1
01H
1
6
Module data width
0
1
0
0
1
0
0
0
48H
72 bits
7
Module data width continuation
0
0
0
0
0
0
0
0
00H
0 (+)
8
Voltage interface level of this assembly 0
0
0
0
0
1
0
0
04H
SSTL 2.5V
9
DDR SDRAM cycle time, CL = X
-6B
0
1
1
0
0
0
0
0
60H
CL = 2.5*
3
-7A, -7B
0
1
1
1
0
1
0
1
75H
10
SDRAM access from clock (tAC)
-6B
0
1
1
1
0
0
0
0
70H
0.70ns*
3
-7A, -7B
0
1
1
1
0
1
0
1
75H
0.75ns*
3
11
DIMM configuration type
0
0
0
0
0
0
1
0
02H
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82H
7.8 µs
Self refresh
13
Primary SDRAM width
0
0
0
0
0
1
0
0
04H
× 4
14
Error checking SDRAM width
0
0
0
0
0
1
0
0
04H
× 4
15
SDRAM device attributes:
Minimum clock delay back-to-back
column access
0
0
0
0
0
0
0
1
01H
1 CLK
16
SDRAM device attributes:
Burst length supported
0
0
0
0
1
1
1
0
0EH
2, 4, 8
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
4
18
SDRAM device attributes:
/CAS latency
0
0
0
0
1
1
0
0
0CH
2, 2.5
19
SDRAM device attributes:
/CS latency
0
0
0
0
0
0
0
1
01H
0
20
SDRAM device attributes:
/WE latency
0
0
0
0
0
0
1
0
02H
1
21
SDRAM module attributes
0
0
1
0
0
1
1
0
26H
Registered
22
SDRAM device attributes: General
1
1
0
0
0
0
0
0
C0H
± 0.2V
Minimum clock cycle time at CLX - 0.5
-6B, -7A
0
1
1
1
0
1
0
1
75H
23
-7B
1
0
1
0
0
0
0
0
A0H
CL = 2*
3
24
Maximum data access time (tAC) from
clock at CLX - 0.5
-6B
0
1
1
1
0
0
0
0
70H
0.70ns*
3
-7A, -7B
0
1
1
1
0
1
0
1
75H
0.75ns*
3
25
Minimum clock cycle time at CLX - 1
0
0
0
0
0
0
0
0
00H
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00H
27
Minimum row precharge time (tRP)
-6B
0
1
0
0
1
0
0
0
48H
18ns
-7A, -7B
0
1
0
1
0
0
0
0
50H
20ns


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