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EBD26UC6AKSA-E Datasheet(PDF) 1 Page - Elpida Memory

Description  256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBD26UC6AKSA-E Datasheet(HTML) 1 Page - Elpida Memory

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Document No. E0605E10 (Ver. 1.0)
Date Published November 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2004
EBD26UC6AKSA-E (32M words
× 64 bits, 2 Ranks)
The EBD26UC6AKSA is 32M words
× 64 bits, 2 ranks
Double Data Rate (DDR) SDRAM Small Outline Dual
In-line Memory Module, mounting 8 pieces of 256M
bits DDR SDRAM sealed in TSOP package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
• 200-pin socket type small outline dual in line memory
module (SO-DIMM)
 PCB height: 31.75mm
 Lead pitch: 0.6mm
 Lead-free
• 2.5V power supply
• Data rate: 333Mbps/266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs, outputs and DM are synchronized with
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: (8192 refresh cycles /64ms)
 7.8µs maximum average periodic refresh interval
• 2 variations of refresh
 Auto refresh
 Self refresh

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