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EBD25UC8AKFA-5-E Datasheet(PDF) 12 Page - Elpida Memory

Part No. EBD25UC8AKFA-5-E
Description  256MB Unbuffered DDR SDRAM DIMM (32M words X 64 bits, 1 Rank)
Download  19 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBD25UC8AKFA-5-E Datasheet(HTML) 12 Page - Elpida Memory

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EBD25UC8AKFA-5-E
Preliminary Data Sheet E0602E10 (Ver. 1.0)
12
Pin Capacitance (TA = 25°C, VDD = 2.6V ± 0.1V)
Parameter
Symbol
Pins
max.
Unit
Note
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/CS, CKE
70
pF
Input capacitance
CI2
CK, /CK
50
pF
Data and DQS input/output
capacitance
CO
DQ, DQS, DM
10
pF
AC Characteristics (TA = 0 to +70
°°°°C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V)
(DDR SDRAM Component Specification)
-5B
-5C
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Clock cycle time
tCK
5
8
5
8
ns
10
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min
(tCH, tCL)
min
(tCH, tCL)
tCK
DQ output access time from CK, /CK
tAC
–0.7
0.7
–0.7
0.7
ns
2, 11
DQS output access time from CK, /CK
tDQSCK
–0.55
0.55
–0.55
0.55
ns
2, 11
DQS to DQ skew
tDQSQ
0.4
0.4
ns
3
DQ/DQS output hold time from DQS
tQH
tHP – tQHS —
tHP – tQHS —
ns
Data hold skew factor
tQHS
0.5
0.5
ns
Data-out high-impedance time
from CK, /CK
tHZ
0.7
0.7
ns
5, 11
Data-out low-impedance time
from CK, /CK
tLZ
–0.7
0.7
–0.7
0.7
ns
6, 11
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
DQ and DM input setup time
tDS
0.4
0.4
ns
8
DQ and DM input hold time
tDH
0.4
0.4
ns
8
DQ and DM input pulse width
tDIPW
1.75
1.75
ns
7
Write preamble setup time
tWPRES
0
0
ns
Write preamble
tWPRE
0.25
0.25
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
9
Write command to first DQS latching
transition
tDQSS
0.72
1.28
0.72
1.28
tCK
DQS falling edge to CK setup time
tDSS
0.2
0.2
tCK
DQS falling edge hold time from CK
tDSH
0.2
0.2
tCK
DQS input high pulse width
tDQSH
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
tCK
Address and control input setup time
tIS
0.6
0.6
ns
8
Address and control input hold time
tIH
0.6
0.6
ns
8
Address and control input pulse width
tIPW
2.2
2.2
ns
7
Mode register set command cycle time
tMRD
2
2
tCK
Active to Precharge command period
tRAS
40
120000
40
120000
ns
Active to Active/Auto refresh command
period
tRC
55
60
ns


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