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EBD25UC8AKFA-5-E Datasheet(PDF) 1 Page - Elpida Memory

Part No. EBD25UC8AKFA-5-E
Description  256MB Unbuffered DDR SDRAM DIMM (32M words X 64 bits, 1 Rank)
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Maker  ELPIDA [Elpida Memory]
Homepage  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBD25UC8AKFA-5-E Datasheet(HTML) 1 Page - Elpida Memory

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Document No. E0602E
10 (Ver. 1.0)
Date Published October 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004
PRELIMINARY DATA SHEET
256MB Unbuffered DDR SDRAM DIMM
EBD25UC8AKFA-5-E (32M words
×××× 64 bits, 1 Rank)
Description
The EBD25UC8AKFA is 32M words
× 64 bits, 1 rank
Double Data Rate (DDR) SDRAM unbuffered module,
mounting 8 pieces of 256M bits DDR SDRAM sealed in
TSOP package.
Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits
prefetch-pipelined architecture.
Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable.
This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
• 184-pin socket type dual in line memory module
(DIMM)
 PCB height: 31.75mm
 Lead pitch: 1.27mm
 Lead-free
• 2.5 V power supply
• Data rate: 400Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Components)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 3
• Programmable output driver strength: normal/weak
• Refresh cycles: (8192 refresh cycles /64ms)
 7.8µs maximum average periodic refresh interval
• 2 variations of refresh
 Auto refresh
 Self refresh


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