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EBD25EC8AKFA-5 Datasheet(PDF) 5 Page - Elpida Memory

Part No. EBD25EC8AKFA-5
Description  256MB Unbuffered DDR SDRAM DIMM (32M words X72 bits, 1 Rank)
Download  19 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBD25EC8AKFA-5 Datasheet(HTML) 5 Page - Elpida Memory

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EBD25EC8AKFA-5
Preliminary Data Sheet E0354E30 (Ver. 3.0)
5
Serial PD Matrix
Byte No.
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
128 bytes
1
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
256 bytes
2
Memory type
0
0
0
0
0
1
1
1
07H
DDR SDRAM
3
Number of row address
0
0
0
0
1
1
0
1
0DH
13
4
Number of column address
0
0
0
0
1
0
1
0
0AH
10
5
Number of DIMM ranks
0
0
0
0
0
0
0
1
01H
1
6
Module data width
0
1
0
0
1
0
0
0
48H
72 bits
7
Module data width continuation
0
0
0
0
0
0
0
0
00H
0
8
Voltage interface level of this assembly 0
0
0
0
0
1
0
0
04H
SSTL2
9
DDR SDRAM cycle time, CL = 3
0
1
0
1
0
0
0
0
50H
5.0ns
*1
10
SDRAM access from clock (tAC)
0
1
1
1
0
0
0
0
70H
0.7ns
*1
11
DIMM configuration type
0
0
0
0
0
0
1
0
02H
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82H
7.8
µs
13
Primary SDRAM width
0
0
0
0
1
0
0
0
08H
× 8
14
Error checking SDRAM width
0
0
0
0
1
0
0
0
08H
× 8
15
SDRAM device attributes:
Minimum clock delay back-to-back
column access
0
0
0
0
0
0
0
1
01H
1 CLK
16
SDRAM device attributes:
Burst length supported
0
0
0
0
1
1
1
0
0EH
2,4,8
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
4
18
SDRAM device attributes:
/CAS latency
0
0
0
1
1
1
0
0
1CH
2, 2.5, 3
19
SDRAM device attributes:
/CS latency
0
0
0
0
0
0
0
1
01H
0
20
SDRAM device attributes:
/WE latency
0
0
0
0
0
0
1
0
02H
1
21
SDRAM module attributes
0
0
1
0
0
0
0
0
20H
Differential
Clock
22
SDRAM device attributes: General
1
1
0
0
0
0
0
0
C0H
VDD ± 0.2V
23
Minimum clock cycle time at CL = 2.5 0
1
1
0
0
0
0
0
60H
6.0ns
*1
24
Maximum data access time (tAC) from
clock at CL = 2.5
0
1
1
1
0
0
0
0
70H
0.7ns
*1
25
Minimum clock cycle time at CL = 2
0
1
1
1
0
1
0
1
75H
0.75ns
*1
26
Maximum data access time (tAC) from
clock at CL = 2
0
1
1
1
0
1
0
1
75H
0.75ns
*1
27
Minimum row precharge time (tRP)
-5B
0
0
1
1
1
1
0
0
3CH
15ns
-5C
0
1
0
0
1
0
0
0
48H
18ns
28
Minimum row active to row active
delay (tRRD)
0
0
1
0
1
0
0
0
28H
10ns
29
Minimum /RAS to /CAS delay (tRCD)
-5B
0
0
1
1
1
1
0
0
3CH
15ns
-5C
0
1
0
0
1
0
0
0
48H
18ns
30
Minimum active to precharge time
(tRAS)
0
0
1
0
1
0
0
0
28H
40ns
31
Module rank density
0
1
0
0
0
0
0
0
40H
256M bytes


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