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IDT72V3623 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT72V3623
Description  3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING 256 x 36, 512 x 36, 1,024 x 36
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V3623 Datasheet(HTML) 1 Page - Integrated Device Technology

 
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1
2001
Integrated Device Technology, Inc. All rights reserved. Product specifications sunject to change without notice.
DSC-4662/3
AUGUST 2001
3.3 VOLT CMOS SyncFIFOTM
WITH BUS-MATCHING
256 x 36, 512 x 36,
1,024 x 36
IDT72V3623
IDT72V3633
IDT72V3643
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
.EATURES:
••••• Memory storage capacity:
IDT72V3623–256 x 36
IDT72V3633–512 x 36
IDT72V3643–1,024 x 36
••••• Clock frequencies up to 100 MHz (6.5 ns access time)
••••• Clocked FIFO buffering data from Port A to Port B
••••• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
••••• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
••••• Serial or parallel programming of partial flags
••••• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
••••• Big- or Little-Endian format for word and byte bus sizes
••••• Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
••••• Mailbox bypass registers for each FIFO
••••• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
••••• Easily expandable in width and depth
••••• Auto power down minimizes power dissipation
••••• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
••••• Pin and functionally compatible versions of the 5V operating
IDT723623/723633/723643
••••• Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
.UNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Programmable Flag
Offset Registers
Status Flag
Logic
EF/OR
AE
36
FF/IR
AF
36
Timing
Mode
FWFT
A0-A35
SPM
FS0/SD
FS1/
SEN
B0-B35
Write
Pointer
Read
Pointer
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
10
4662 drw01
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
FIFO1
Mail1,
Mail2,
Reset
Logic
RS1
MBF1
36
PRS
36
36
RS2
36


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