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IDT72V3623 Datasheet(PDF) 26 Page - Integrated Device Technology |
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IDT72V3623 Datasheet(HTML) 26 Page - Integrated Device Technology |
26 / 28 page 26 IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING 256 x 36, 512 x 36, 1,024 x 36 COMMERCIAL TEMPERATURERANGE Figure 18. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes) NOTE: 1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don't care inputs). In this second case, A0-A8 will have valid data (A9-A35 will be indeterminate). Figure 19. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration NOTES: 1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND) 2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster. 3. The amount of time it takes for EF/OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period. 4. The amount of time it takes for FF/IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO: (N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period. 4662 drw20 CLKB ENB B0-B35 MBB CSB W/RB CLKA MBF2 CSA MBA ENA A0-A35 W/ RA tENH tDS tDH tENH tDIS tEN tMDV tPMR FIFO Output Register W1 (Remains valid in Mail2 Register after read) tENH tENH tENH tPMF tPMF W1 tENS2 tENS1 tENS2 tENS2 tENS2 DATA IN (Dn) READ CLOCK (CLKB) READ ENABLE (ENB) EMPTY FLAG/ OUTPUT READY ( EF/OR) CHIP SELECT ( CSB) DATA OUT (Qn) TRANSFER CLOCK 4662 drw21 IDT 72V3623 72V3633 72V3643 VCC IDT 72V3623 72V3633 72V3643 WRITE READ A0-A35 MBA CHIP SELECT ( CSA) WRITE SELECT (W/ RA) WRITE ENABLE (ENA) ALMOST-FULL FLAG ( AF) FULL FLAG/ INPUT READY ( FF/IR) WRITE CLOCK (CLKA) CLKB EF/OR ENB CSB B0-B35 W/RB MBB CLKA ENA FF/IR CSA MBA A0-A35 W/ RA READ SELECT ( W/RB) ALMOST-EMPTY FLAG ( AE) B0-B35 MBB VCC n n n Qn Dn VCC VCC |
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