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CY7C026V Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C026V
Description  3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C026V Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C024V/025V/026V
CY7C0241V/0251V/036V
7
PRELIMINARY
Switching Characteristics Over the Operating Range[13]
Parameter
Description
CY7C024V/025V/026V
CY7C0241V/0251V/036V
Unit
-15[1]
-20
-25
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
15
20
25
ns
tAA
Address to Data Valid
15
20
25
ns
tOHA
Output Hold From Address Change
3
3
3
ns
tACE
[14]
CE LOW to Data Valid
15
20
25
ns
tDOE
OE LOW to Data Valid
10
12
13
ns
tLZOE
[15, 16, 17]
OE Low to Low Z
3
3
3
ns
tHZOE
[15, 16, 17]
OE HIGH to High Z
10
12
15
ns
tLZCE
[15, 16, 17]
CE LOW to Low Z
3
3
3
ns
tHZCE
[15, 16, 17]
CE HIGH to High Z
10
12
15
ns
tPU
[17]
CE LOW to Power-Up
0
0
0
ns
tPD
[17]
CE HIGH to Power-Down
15
20
25
ns
tABE
[14]
Byte Enable Access Time
15
20
25
ns
WRITE CYCLE
tWC
Write Cycle Time
15
20
25
ns
tSCE
[14]
CE LOW to Write End
12
15
20
ns
tAW
Address Valid to Write End
12
15
20
ns
tHA
Address Hold From Write End
0
0
0
ns
tSA
[14]
Address Set-Up to Write Start
0
0
0
ns
tPWE
Write Pulse Width
12
15
20
ns
tSD
Data Set-Up to Write End
10
15
15
ns
tHD
Data Hold From Write End
0
0
0
ns
tHZWE
[16, 17]
R/W LOW to High Z
10
12
15
ns
tLZWE
[16, 17]
R/W HIGH to Low Z
3
3
0
ns
tWDD
[18]
Write Pulse to Data Delay
30
45
50
ns
tDDD
[18]
Write Data Valid to Read Data Valid
25
30
35
ns
Notes:
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
14. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
15. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
16. Test conditions used are Load 3.
17. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.


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