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LPC47M112 Datasheet(PDF) 23 Page - SMSC Corporation

Part No. LPC47M112
Description  ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
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Maker  SMSC [SMSC Corporation]
Homepage  http://www.smsc.com
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Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS – LPC47M112
Page 23
Rev. 02/02/2005
DATASHEET
8.3.3.4
DMA Protocol
DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47M112 and special encodings on
LAD[3:0] from the host.
The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification, Revision 1.0.
8.4 Power Management
8.4.1
CLOCKRUN PROTOCOL
The nCLKRUN pin is not implemented in the LPC47M112. See the Low Pin Count (LPC) Interface Specification
Section.
8.4.1.1
LPCPD Protocol
See the Low Pin Count (LPC) Interface Specification Section.
8.4.1.2
SYNC Protocol
See the Low Pin Count (LPC) Interface Specification Section for a table of valid SYNC values.
8.4.2
TYPICAL USAGE
The SYNC pattern is used to add wait states. For read cycles, the LPC47M112 immediately drives the SYNC pattern
upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M112 needs
to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or
1001. The LPC47M112 will choose to assert 0101 or 0110, but not switch between the two patterns.
The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.
The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few
clocks. The LPC47M112 uses a SYNC of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP
cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47M112 uses a
SYNC of 0110 for all wait states in an I/O transfer.
The SYNC value is driven within 3 clocks.
8.4.3
SYNC TIMEOUT
The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it
will abort the cycle.
The LPC47M112 does not assume any particular timeout. When the host is driving SYNC, it may have to insert a
very large number of wait states, depending on PCI latencies and retries.
8.4.4
SYNC PATTERNS AND MAXIMUM NUMBER OF SYNCS
If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.
If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M112 has protection
mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout
protection that is in EPP.
8.4.5
SYNC ERROR INDICATION
The LPC47M112 reports errors via the LAD[3:0] = 1010 SYNC encoding.




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