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74LVC74A-Q100 Datasheet(PDF) 7 Page - Nexperia B.V. All rights reserved |
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74LVC74A-Q100 Datasheet(HTML) 7 Page - Nexperia B.V. All rights reserved |
7 / 18 page ![]() © Nexperia B.V. 2017. All rights reserved 74LVC74A_Q100 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 5 April 2013 7 of 18 Nexperia 74LVC74A-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max tpd propagation delay nCP to nQ, nQ; see Figure 7 [2] VCC = 1.2 V - 15 - - - ns VCC = 1.65 V to 1.95 V 1.0 5.0 10.3 1.0 11.9 ns VCC = 2.3 V to 2.7 V 1.8 2.9 5.8 1.8 6.7 ns VCC = 2.7 V 1.0 2.7 6.0 1.0 7.5 ns VCC = 3.0 V to 3.6 V 1.0 2.6 5.2 1.0 6.5 ns nSDtonQ, nQ; see Figure 8 VCC = 1.2 V - 15 - - - ns VCC = 1.65 V to 1.95 V 0.5 4.0 10.6 0.5 12.2 ns VCC = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns VCC = 2.7 V 1.0 2.9 6.4 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns nRD to nQ, nQ; see Figure 8 VCC = 1.2 V - 15 - - - ns VCC = 1.65 V to 1.95 V 0.5 4.1 10.7 0.5 12.4 ns VCC = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns VCC = 2.7 V 1.0 3.0 6.4 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns tW pulse width clock HIGH or LOW; see Figure 7 VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.3 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns set or reset LOW; see Figure 8 VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.3 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns trec recovery time set or reset; see Figure 8 VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns VCC = 2.3 V to 2.7 V 1.5 - - 1.5 - ns VCC = 2.7 V 1.5 - - 1.0 - ns VCC = 3.0 V to 3.6 V +1.0 3.0 - 1.0 - ns |
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