© Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 1

1

Publication Order Number:

MC10EP33/D

MC10EP33

B4 Divider

The MC10EP33 is an integrated

B4 divider. The differential clock

inputs and the VBB allow a differential, single–ended or AC coupled

interface to the device. If used, the VBB output should be bypassed to

ground with a 0.01

µF capacitor.

The reset pin is asynchronous and is asserted on the rising edge.

Upon power–up, the internal flip–flops will attain a random state; the

reset allows for the synchronization of multiple EP33’s in a system.

Oxygen Index 28 to 34

1

2

3

45

6

7

8

Q

VEE

VCC

Figure 1. 8–Lead Pinout (Top View) and Logic Diagram

CLK

Q

CLK

VBB

RESET

R

B4

SO–8

D SUFFIX

CASE 751

PIN DESCRIPTION

PIN

CLK, CLK

Reset

ECL Asynchronous Reset

FUNCTION

ECL Clock Inputs

http://onsemi.com

TRUTH TABLE

CLK

X

Z

CLK

X

Z

RESET

Z

L

Q

L

F

Q

H

F

Z = LOW to HIGH Transition

Z = HIGH to LOW Transition

F = Divide by 4 Function

VBB

Reference Voltage Output

Q, Q

ECL Data Outputs

MARKING DIAGRAM

Device

Package

Shipping

ORDERING INFORMATION

MC10EP33D

SOIC

98 Units/Rail

MC10EP33DR2

SOIC

2500 Tape & Reel

VCC

Positive Supply

VEE

Negative, 0 Supply

ALYW

HEP33

1

8

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

*For additional information, see Application Note

AND8002/D

1

8