ADE7763 datasheet(28/56 Pages) AD

Part #	ADE7763

Description	Single-Phase Active and Apparent Energy Metering IC

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ADE7763

Rev. A | Page 28 of 56

Integration Time under Steady Load

As mentioned in the last section, the discrete time sample

period (

T) for the accumulation register is 1.1 µs (4/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

WGAIN register set to 0x000, the average word value from each

LPF2 is 0xC CCCD—see Figure 53. The maximum positive

value that can be stored in the internal 49-bit register before it

overflows is 248, or 0xFFFF FFFF FFFF. The integration time

under these conditions with WDIV = 0 is calculated as follows:

Time =

min

26

.

6

s

8

.

375

s

12

.

1

CCCD

0xC

FFFF

0xFFFF

=

µ

×

(15)

When WDIV is set to a value other than 0, the integration time

varies, as shown in Equation 16.

Time

= TimeWDIV = 0 × WDIV

(16)

POWER OFFSET CALIBRATION

The ADE7763 incorporates an active power offset register

(APOS[15:0]). This is a signed, twos complement, 16-bit

register that can be used to remove offsets in the active power

calculation—see Figure 57. An offset could exist in the power

calculation due to crosstalk between channels on the PCB or in

the IC itself. The offset calibration allows the contents of the

active power register to be maintained at 0 when no power is

being consumed.

The 256 LSBs (APOS = 0x0100) written to the active power

offset register are equivalent to 1 LSB in the waveform sample

register. Assuming the average value output from LPF2 is

0xC CCCD (838,861d) when inputs on Channels 1 and 2 are

both at full scale. At −60 dB down on Channel 1 (1/1000 of the

Channel 1 full-scale input), the average word value output from

LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output

has a measurement error of 1/838.861 × 100% = 0.119% of the

average value. The active power offset register has a resolution

equal to 1/256 LSB of the waveform register; therefore, the

power offset correction resolution is 0.00047%/LSB

(0.119%/256) at –60 dB.

ENERGY-TO-FREQUENCY CONVERSION

The ADE7763 provides energy-to-frequency conversion for

calibration purposes. After initial calibration at manufacturing,

the manufacturer or end customer often verifies the energy meter

calibration. One convenient way to verify the meter calibration

is for the manufacturer to provide an output frequency, which is

proportional to the energy or active power under steady load

conditions. This output frequency can provide a simple, single-

wire, optically isolated interface to external calibration equip-

ment. Figure 59 illustrates the energy-to-frequency conversion.

CFNUM[11:0]

CF

11

0

CFDEN[11:0]

11

0

AENERGY[48:0]

480

%

DFC

Figure 59. Energy-to-Frequency Conversion

A digital-to-frequency converter (DFC) is used to generate the

CF pulsed output. The DFC generates a pulse each time 1 LSB

in the active energy register is accumulated. An output pulse is

generated when (CFDEN + 1)/(CFNUM + 1) number of pulses

are generated at the DFC output. Under steady load conditions,

the output frequency is proportional to the active power.

The maximum output frequency, with ac input signals at full

scale, CFNUM = 0x00, and CFDEN = 0x00, is approximately

23 kHz.

There are two unsigned, 12-bit registers, CFNUM[11:0] and

CFDEN[11:0], that can be used to set the CF frequency to a wide

range of values. These frequency-scaling registers are 12-bit

registers that can scale the output frequency by 1/212 to 1 with a

step of 1/212.

If the value 0 is written to any of these registers, the value 1 will

be applied to the register. The ratio (CFNUM + 1)/(CFDEN + 1)

should be smaller than 1 to ensure proper operation. If the ratio

of the registers (CFNUM + 1)/(CFDEN + 1) is greater than 1, the

register values will be adjusted to a ratio (CFNUM + 1)/

(CFDEN + 1) of 1. For example, if the output frequency is

1.562 kHz while the contents of CFDEN are 0 (0x000), then the

output frequency can be set to 6.1 Hz by writing 0xFF to the

CFDEN register.

When CFNUM and CFDEN are both set to one, the CF pulse

width is fixed at 16 CLKIN/4 clock cycles, approximately 18 µs

with a CLKIN of 3.579545 MHz. If the CF pulse output is longer

than 180 ms for an active energy frequency of less than 5.56 Hz,

the pulse width is fixed at 90 ms. Otherwise, the pulse width is

50% of the duty cycle.

The output frequency has a slight ripple at a frequency equal to

twice the line frequency. This is due to imperfect filtering of the

instantaneous power signal to generate the active power signal—

see the Active Power Calculation section. Equation 8 gives an

expression for the instantaneous power signal. This is filtered by

LPF2, which has a magnitude response given by Equation 17.

2

9

.

8

1

)

(

2

f

H

+

=

(17)

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