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M5M532R16J-10 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor

Part No. M5M532R16J-10
Description  524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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M5M532R16J-10 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor

   
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M5M532R16J,TP-10,-12,-15
MITSUBISHI LSIs
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
1
Outline
44P0K(J)
44P3W-H(TP)
PIN CONFIGURATION (TOP VIEW)
1997.01.22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FEATURES
Fast access time
M5M532R16J,TP-10
10ns(max)
M5M532R16J,TP-12
12ns(max)
M5M532R16J,TP-15
15ns(max)
Low power dissipation
Active
500mW(typ)
Stand by
15mW(typ)
Single +5V power supply
Fully static operation : No clocks, No refresh
Common data I/O
Easy memory expansion by /S
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Directly TTL compatible : All inputs and outputs
Separate control of lower and upper bytes by /LB and /UB
DESCRIPTION
The M5M532R16 is a family of 32768-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 5V supply, and are directly
TTL compatible.
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by /LB
and /UB.
APPLICATION
High-speed memory system
DQ1
ADDRESS
INPUTS
CHIP
SELECT
INPUTS
DATA
INPUTS/
OUTPUTS
DATA
INPUTS/
OUTPUTS
WRITE
CONTROL
INPUT
ADDRESS
INPUTS
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
DATA
INPUTS/
OUTPUTS
BYTE
CONTROL
INPUTS
ADDRESS
INPUTS
1
N.C
FUNCTION
The operation mode of the M5M532R16 is determined
by a combination of the device control inputs /S, /W,
/OE, /LB, and /UB. Each mode is summarized in the
function table.
A write cycle is executed whenever the low level /W
overlaps with low level /LB and/or low level /UB and low
level /S. The address must be set-up before write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the traling edge of
/W, /LB, /UB or /S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input /OE directly
controls the output stage. Setting the /OE at a high
level, the output stage is in a high impedance state, and
the data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and /OE at a low level while /LB and/or /UB and /S are
in an active state. (/LB and/or /UB=L, /S=L)
When setting /LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting /UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and
upper-Byte are in a non-selectable mode.
When setting /LB and /UB at a high level or /S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing
OR-tie
with
other
chips
and
memory
expansion by /LB, /UB and /S.
Signal-/S controls the power-down feature. When /S
goes high, power dissapation is reduced extremely.
The access time from /S is equivalent to the address
access time.
PACKAGE
M5M532R16J : 44pin 400mil SOJ
M5M532R16VP: 44pin 400mil TSOP(II)
2
A3
3
4
A2
A1
5
A0
6
/S
7
8
DQ2
DQ3
9
DQ4
10
Vcc
11
GND
12
(5V)
(0V)
DQ5
13
14
DQ6
DQ7
15
DQ8
16
17
/W
18
A14
19
20
A13
A12
21
A11
22
NC
DQ16
A4
A5
A6
/OE
/UB
/LB
DQ15
DQ14
DQ13
35
GND
34
Vcc
33
DQ12
32
31
DQ11
DQ10
30
DQ9
29
28
NC
27
A7
26
25
A8
A9
24
A10
23
NC
36
35
38
39
40
41
42
43
44
OUTPUT
ENABLE
(0V)
(5V)


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